COA Preparation

• Computer Architecture and Organization

• IBM 370

• Differences between Structure and function

• Computer

• A top-down view of a computer

• Simplified view of Major elements of a multicore computer

• Computer Generations differences

• IAS Structure

• Registers
  • MBR : Memory Buffer Register
    • Contains a word to be stored/received in/from memory or sent to/from the I/O input.
  • MAR : Memory Address Register
    • Specifies the address in memory of the word to be written from or read into the MBR
  • IR : Instruction Register
    • Contains the 8 bit opcode instruction being executed
  • IBR : Instruction Buffer Register
    • Employed to temporarily hold the right hand instruction from a word in memory
  • PC : Program Counter
    • Contains the address of the next instruction pair to be fetched from memory
  • Accumulator (AC) and Multiplier Quotient (MQ):
    • Employed to temporarily hold operands and results of ALU operations

• IBM 7094 Configuration

• Moore’s Law and it’s consequence

Moore’s Law: Number of transistors that could be put on a single chip was doubling every year.

Consequences:

• The cost of computer logic and memory circuitry has fallen at a dramatic rate

• The electrical path length is shortened increasing operating speed.

• Computer becomes smaller and it more convenient to use in a variety of environments.

• Reduction in power and cooling requirements.

• Fewer interchip connection.

• Basic Instruction Cycle

• Fetch Cycle
  • The processor fetches an instruction from memory
  • The PC holds the address of the instruction to be fetched next
  • The processor increment the PC after each instruction fetch
  • The fetched instruction is loaded into the IR
  • The processor interprets the instruction and perform the required action.

• Computer Components : Top-Level View

• Action categories
  • Processor memory : Data may be transferred from processor to memory or from memory to processor.
  • Processor I/O: Data maybe transferred to or from a peripheral device by transferring between the processor and I/O module.
  • Data Processing: The processor may perform some arithmetic or logic operation on data.
  • Control: An instruction may specify that the sequence be altered. For example, the processor may fetch an instruction from location 149, which specifies that he next instruction be from location 182. The processor will remember this fact by setting the program counter to 182 rather than 150.

• Characteristics of a Hypothetical machine

• Program Execution

• Classes of interrupts
  • Program: Generated by some condition occurs as a result of an instruction execution, such as arithmetic overflow, division by zero.
  • Timer: Generated by a timer within processor.
  • I/O: Generated by an I/O controller, to signal normal completion of an operation.
  • Hardware Failure: Generated by a failure such as power failure or memory parity error

• No Interrupt Program flow

• Instruction Cycle with Interrupts

• Transfer of Control via Interrupts

• Instruction Cycle State Diagram with Interrupts

• Transfer of Control with Multiple Interrupts

• Time Sequence of Multiple Interrupts

• I/O Function
  • I/O Module can exchange data directly with the processor
  • Processor can read data from or write data to an I/O module
  • In some cases it is desirable to allow I/O exchanges to occur directly with memory (known as Direct Memory Access DMA)

  

• Bus

A communication pathway connecting two or more devices.

• Bus Interconnection Scheme

• Interconnection Structure
  • Memory to Processor : the processor reads an instruction from memory
  • Processor to memory: the processor writes a unit of data to memory
  • I/O to processor: the processor reads data from I/O device
  • Processor to I/O : The processor sends data to the I/O
  • I/O to or from memory: For those two cases, an I/O module is allowed to exchange data directly with memory, without going through the processor

• Bus Type
  • Data Bus: carries data, Width is a key determinant of performance (16, 32 bit)
  • Address bus: Identify the source or destination of data
  • Control Bus: Control and timing information, memory signal, Interrupt request, Clock signals

  2

  • Dedicated: Permanently assigned to one function or to a physical subset of computer components
  • Multiplexed: same line used for multiple purpose

• Bus Width
  • The width of a bus is the number of lines. The more data lines, the more data that can be transferred simultaneously.
  • “32 bit bus” → 32 data lines
  • the more address lines → larger the maximum amount of memory that can be accessed
  • the greater the width → the more hardware required

• ISA bus

• High Performance Bus

• Multiplexed Bus Operation

• Synchronous timing diagram

• Asynchronous write diagram

• Bus Arbitration

  Bus arbitration is a process by which another device is selected to become a bus mater.

• Differences between Bus Arbitration

Previous:

• What is addressing mode? Differentiate between a direct and an indirect addressing mode.

Addressing mode: Addressing mode is a basically a technique used for determining the operand that associates with any given instruction.

• Distinguish between RISC and CISC Processor

• Show the instruction pipelining with branch operations. Can Pipelining be a trouble? why? How can we resolve it ?

Instruction Pipelining is a technique used to improve instruction throughout and overall performance by allowing multiple instructions to be processed concurrently.

Handling Branches in instruction pipelining introduces challenges because the next instruction to be fetched may depend on the outcome of a branch instruction.

For Branch Operation

FI → Fetch the instruction from memory

DA → Decode the instruction

FO → Fetch the operands from memory

Ex → Execute the instruction.

Yes, Pipelining be a trouble for several issues and complications. These are:

• Pipeline Hazards
  • Data
  • Control
  • Structural

• Pipeline flush

  Incorrect branch prediction can lead to these type of Hazards

• Clock Speed Limitations

  Deeper Pipelines may face this type of trouble.

The way of resolving:

• Difference Between Half Adder and Full Adder

• Distinguish between SRAM and DRAM

• 4 Bit Ripple carry adder. What is the disadvantage of it ?

Disadvantages:

• It doesn’t allow to use all full adders simultaneously.

• Each full adder has to necessarily wait until the carry bit becomes available,

• This increase propagation time

• It is slow

• What is Parallel processing ? Discuss about the levels parallel processing with proper examples.

Parallel processing is a method in computing of running two or more processor to handle separate parts of an overall task.

Four levels:

• Instruction level : It refers the situation where different instruction of a program are executed by different processing elements. Most processor has several execution units and can execute several instruction at the same time.

• Loop level: At this level consecutive loop iterations are the candidates for parallel execution. There is a lot of scope for parallel execution at loop level.

  Example : in C language,

  for(i=0; i≤n; i++)

  A(i) = B(i)+C(i)

  Each of instruction A(i)=B(i)+C(i) can be executed by different processing element provided. There are at least n processing element.

• Procedure level: here parallelism is available in the form of parallel executable procedures. In this process the design of the algorithm plays a major role. Parallelism at this level is performed using the operating system, but it needs a good programming that helped to perform and analyze this type of parallelism.

• Program level : This is usually the responsibility of the operating system which runs processes concurrently. Different programs are obviously independent of each other. So, parallelism can be extracted by operating of the system at this level.

• Differences between SDRAM and DDR SDRAM

• Derive the equation of 4-bit carry look ahead adder. What are the advantage and disadvantage of it?

Advantage

• It generates the carry-in for each fill adder simultaneously

• It reduces the propagation delay

• It is fastest

Disadvantages

• Complex hardware

• Costlier

• It gets more complicated as the number of bits increase.